Adders and D-Type Flip-Flops

A half-adder combines two one-bit inputs A and B. Its sum output is A XOR B, and its carry output is A AND B. Inputs 1 and 1 therefore give sum 0 and carry 1, representing binary 10 across two output places.

The circuit has no carry-in input, so it cannot by itself process an additional carry from a previous bit column. Constructing the half-adder requires an XOR gate and an AND gate receiving the same two inputs. Sum and carry have different positional weights.

A full-adder accepts A, B and a carry-in. Sum=A XOR B XOR carry-in. A carry-out is true when at least two of the three inputs are true; one expression is (A AND B) OR (carry-in AND (A XOR B)).

Full-adders can be connected so that one bit position’s carry-out becomes the next position’s carry-in. The final carry must be interpreted in the width and signedness model of the complete calculation. A carry wire alone does not decide every signed-overflow question.

An edge-triggered D-type flip-flop captures its D input at the designated active clock edge and retains Q between those edges. In a rising-edge example, a change to D while the clock remains high does not continuously pass through to Q.

This is different from a level-sensitive latch. State the initial Q and whether the edge is rising or falling before tracing a timing table. Explain the flip-flop’s memory behaviour through its input, stored state and active clock edges.

Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.