Counters and Astable Clocks

A binary counter moves through binary-number states on the specified clock edge. An N-bit full binary counter has $2^N$ states. A BCD counter represents decimal digits with four bits and normally cycles from 0000 to 1001 before returning to 0000.

A Johnson counter cycles through a particular sequence of bit patterns by feeding an inverted final stage back to the first. For N stages its usual cycle has 2N states; a decoded device may present one active output at a time. Interpret the supplied timing diagram or block, rather than assuming its visible outputs must be the ordinary binary count.

Clock supplies count events, reset returns the circuit to a defined initial state, and an up/down input selects counting direction when the device supports it. Observe whether reset is active high or active low and whether a clock responds on rising or falling edges.

A modulo-n counter can be built by detecting state n and using logic to reset to zero. For an ideal asynchronous reset, state n is only momentary and the sustained sequence is 0 to n−1. A modulo-6 binary counter can decode 110 to reset. Real propagation delays can produce short pulses, so timing matters in a practical design.

An astable oscillates between high and low without a stable resting state. Its period is high time plus low time; pulse width usually denotes the high interval. Duty cycle is the fraction of the period spent high, while mark-to-space ratio compares high time with low time.

An external RC network sets timing in many astables. Increasing a timing resistance or capacitance generally slows the oscillation when the other parameters are fixed, but use the device’s supplied relation for a numerical calculation. A particular 555 circuit is not required.

Try each problem before opening the worked solution. State the physical model, show substitutions with consistent units, and explain what your answer means.