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Rank memory levels by their role and typical trade-offs. Explain locality and a cache hit/miss without assuming that a larger capacity makes every access faster.
What you'll be able to do
Registers hold immediate processor state and operands, with very small capacity and rapid access. L1 cache is typically the closest, smallest cache level; L2 is often larger, while L3 can be larger again and shared in common multicore arrangements. These are typical design patterns, not a guarantee that every processor has exactly the same number of levels or sharing policy.
Main RAM holds a much larger active working set with longer access latency. Secondary storage retains programs and files persistently and normally offers much greater capacity at a higher access cost. Ordinary registers, caches and DRAM working memory are volatile; persistent secondary storage supplies a different role. Loading a file into RAM does not make the disk itself become a register.
Temporal locality means recently used information may be needed again. Spatial locality means nearby information may be used soon, such as successive array elements or adjacent instructions. A cache can retain blocks so a hit is served from a closer level instead of a slower one. A miss requires obtaining the requested information from another level and may require replacing something already cached.
Cache is a copy-management mechanism rather than unlimited extra main memory. A repeated small working set may benefit substantially, while a stream exceeding the cache or an irregular access pattern can produce more misses. Modified copies need appropriate write/freshness rules. More cache can help a fitting workload, but hit time, organisation and other bottlenecks also affect total execution.
Suppose a simplified cache lookup costs 2 ns. A hit finishes there; a miss adds a further 50 ns to retrieve the item. With a 90% hit rate, mean access cost is 0.9×2+0.1×52=7 ns. The miss cost here includes the initial lookup, so adding 2 ns a second time would double count it. Read whether the question gives an extra penalty or a complete miss time.
The hierarchy trades small fast expensive-per-unit storage against larger slower cheaper-per-unit capacity. A machine with more disk space but insufficient RAM may still move working data frequently, while a CPU with fast arithmetic can wait for memory. A recommendation should connect the workload’s working set, persistence and access pattern to the relevant level, rather than choosing whichever component has the largest advertised number.
| Level | Typical role | Typical capacity/access trade-off |
|---|---|---|
| Registers | Immediate CPU state and operands | Very small and very fast |
| L1 cache | Closest cached copies | Small, low-latency |
| L2/L3 cache | Larger cached working sets | Larger, typically more latency |
| RAM | Active programs/data | Much larger working capacity |
| Secondary storage | Persistent files/programs | High capacity, slower access |
Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.
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Key takeaways
Test yourself
Answer a few questions, then review anything you missed.
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