Stored Programs, Buses and Memory

A stored-program computer represents executable instructions in memory so that a processor can fetch and execute them. Changing the stored instructions can make the same general-purpose hardware perform a different task without rewiring a whole circuit. This flexibility supports software development and reuse, but incorrect or corrupted instructions can also make the machine perform unintended operations.

In a simplified von Neumann organisation, instructions and data share a memory system and access pathway. The CPU interprets the current instruction using its instruction-set rules; the same bit pattern could instead be ordinary data under a different context. Shared memory is flexible, while simultaneous demands for instruction fetches and data access can contend for the limited path.

The CPU executes instructions. RAM supplies volatile working storage for active program/data values; ordinary RAM loses its contents without power. ROM provides non-volatile stored instructions in the traditional firmware model. Modern firmware can use rewritable flash, so non-volatile does not always mean physically impossible to update. Cache keeps copies near the processor to reduce the delay of suitable repeated accesses.

Input/output components exchange information with the outside system, often through controllers and device interfaces. An address bus identifies a selected location or device, a data bus carries values, and a control bus carries coordination signals such as read/write requests. The buses are communication pathways, not additional application storage. Label the signal’s role rather than guessing from its drawn direction alone.

With n independent address bits, at most 2ⁿ distinct addresses can be selected. Capacity also depends on how much data each address names. A byte-addressed system with twenty address bits can select 2²⁰ bytes, or 1 MiB. If each address instead identifies a four-byte word, the same address count describes 4 MiB.

Data-bus width answers a different question about a transfer’s possible size in the stated model. A thirty-two-bit data bus does not automatically mean thirty-two address bits or four gibibytes of addressable RAM. Specify addressable units, available mappings and question assumptions. In a complete system, some address space may also be reserved for devices, so a theoretical maximum is not always the installed usable-memory quantity.

Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.