Loading...
Give each register a distinct role and make every transfer’s source explicit. Use brackets for register contents and state the instruction-width model before incrementing the program counter.
What you'll be able to do
The control unit interprets instructions and coordinates control signals. The ALU performs arithmetic and logical operations. A clock coordinates timed activity; it does not guarantee that every instruction completes in exactly one tick. General-purpose registers retain values for rapid use during computation, while named special-purpose registers serve particular roles in the model.
PC holds the next instruction address; MAR holds the address for a memory access; MBR, also called MDR in some descriptions, holds a transferred word; CIR holds the current instruction; and ACC stores arithmetic results in an accumulator-based model. SP identifies the current stack position under the machine’s convention. SR contains status flags, such as zero or carry, used by relevant operations and branches.
Pearson’s appendix uses square brackets to identify contents: MAR←[PC] means copy the current PC contents into MAR. It does not move the physical PC register. In the teaching table, Memory[address] denotes the value stored at a memory location, and nested Memory[[MAR]] means access the address currently held in MAR. State this notation before tracing it.
Assume byte addresses and fixed four-byte instructions for this example. With PC=400, fetch copies 400 into MAR, asserts a read request, transfers the instruction word through MBR to CIR and advances PC to 404. Another educational model may use one word per address and PC+1; the increment is determined by instruction width and address unit rather than a universal rule.
Decoding identifies the instruction’s operation and operand meaning. Execution may update registers, request another memory read/write, change status flags or branch by replacing PC. A write operation supplies both the target address and a data value with the appropriate write-control signal. The program counter’s sequential advance does not guarantee the next fetch remains sequential after a taken branch.
A call stack retains state needed by nested subprogram calls, potentially including return information, parameters and local values under the chosen model. SP is not itself a copy of every stack frame. In a trace, record each changed value and its cause, including read/write control and any branch update. Comparing only the final arithmetic answer can miss a transfer from the wrong source register.
| Step | Transfer or action | Meaning in the stated model |
|---|---|---|
| 1 | MAR ← [PC] | Select byte address 400 |
| 2 | Assert READ | Request the word at the selected address |
| 3 | MBR ← Memory[[MAR]] | Receive the instruction word |
| 4 | CIR ← [MBR] | Retain the fetched instruction |
| 5 | PC ← [PC] + 4 | Prepare sequential address 404 |
| 6 | Decode and execute [CIR] | Apply the instruction; a branch may replace PC |
Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.
Common mistakes to avoid
Key takeaways
Test yourself
Answer a few questions, then review anything you missed.
Start with the quiz above to check the key ideas. You can also choose another topic from the practice library.