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4.7.1.1, 4.7.2.1Organisation and ArchitectureCore
Buses, Memory and Computer Architectures
A processor communicates with memory and devices through defined pathways. Explain which quantity travels along each pathway and how instruction and data storage are organised.
What you'll be able to do
- Describe processor, memory, buses and I/O controllers
- Calculate addressable locations under explicit assumptions
- Compare von Neumann and Harvard organisation
1
Connect the main components
The processor executes instructions, main memory holds accessible program/data values, and input/output controllers mediate communication with devices. An address bus identifies a location or target, a data bus carries values, and control signals coordinate operations such as read, write and timing.
A bus is a shared communication pathway under the system’s rules, not a separate storage area for an entire application. An I/O controller can buffer data and handle device-specific signalling so that the processor interacts through a suitable interface rather than directly managing every physical detail.
2
Distinguish addressing from transfer width
With n address bits, up to 2ⁿ distinct locations can be selected. The amount of addressable data also depends on the size of each location. A byte-addressed model and a word-addressed model give different byte capacities for the same number of addresses.
Data bus width affects how many bits can be transferred together under the stated transfer model. It does not by itself determine the number of possible memory addresses. Main memory, cache and secondary storage also have different roles; a large disk does not automatically mean every disk byte is directly addressable as main memory.
3
Compare stored-program organisations
The stored-program principle keeps executable instructions in memory so that the processor can fetch and execute them. A basic von Neumann organisation shares instruction and data memory and pathways. This can create contention when both need transfer resources.
Harvard organisation separates instruction and data storage/pathways, allowing different access arrangements and simultaneous activity where supported. It is useful in contexts such as embedded signal processing. Real processors can combine ideas, so the simplified models explain structure without asserting that every modern chip fits one pure diagram.
| Pathway | Main role |
|---|---|
| Address bus | Select a location |
| Data bus | Transfer values |
| Control bus/signals | Coordinate operations |
| I/O controller | Interface to a device |
4
Work through the problem
Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.
Example 1A byte-addressed model has 20 address bits. What is its addressable capacity?
12²⁰ locations are available.
2Each location holds one byte, giving 1048576 bytes.
Answer1 MiB.
Example 2Would 20 address bits always imply 1 MiB if each location held four bytes?
1The location count stays 2²⁰.
2Four bytes per location gives 4×2²⁰ bytes.
AnswerNo; that model addresses 4 MiB.
Common mistakes to avoid
Equating address bits with a byte capacity without checking the addressable unit.
Calculate locations first, then bytes.
Confusing data-bus width with address-bus width.
Separate transfer size from location selection.
Key takeaways
- Buses carry addresses, values and control information.
- Address count and location width determine capacity.
- Architecture models organise instruction and data access.
Test yourself
Answer a few questions, then review anything you missed.
Next step
Browse practice topicsKeep practising
Start with the quiz above to check the key ideas. You can also choose another topic from the practice library.