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A processor must respond to events while preserving unfinished work. Its performance also depends on the workload and the entire memory/transfer path, not just one advertised clock frequency.
What you'll be able to do
An interrupt signals that an event requires attention, such as completed I/O or a timer event. Under the processor’s rules, execution can transfer to an interrupt service routine. Relevant volatile context, including return location, registers and status, must be preserved so the original task can resume correctly.
The ISR handles the event and restores or arranges restoration of that context before return. Interrupt priority and masking policies determine which events can be handled when. Avoid claiming that every interrupt occurs halfway through an arbitrary instruction or that the original program automatically restarts from its beginning.
A higher clock rate can provide more cycles per second, but instructions need not all take one cycle or do equal work across different architectures. Multiple cores can run independent work in parallel when the software and workload permit it; serial dependencies limit the benefit.
Cache reduces average access cost when useful instructions and data are reused or accessed near recently used locations. A larger cache is not an automatic guarantee of a particular speed-up. Word length affects representable native values and operations, but overall performance still depends on the computation and architecture.
A wider address bus can permit more addressable locations, subject to the addressing model. A wider data bus can transfer more bits per bus operation, subject to timing and device limits. These are different effects and should not be conflated into a single “more memory” claim.
A program waiting for storage or network data may gain little from a faster arithmetic unit. Compare systems on a representative task and explain the limiting resource. Benchmark results are evidence for stated conditions, while complexity describes a different question about scaling with input size.
| Factor | Potential benefit | Qualification |
|---|---|---|
| More cores | More parallel work | Needs parallelisable tasks |
| Faster clock | More cycles per second | Work per cycle and stalls vary |
| Cache | Fewer slow accesses | Depends on access patterns |
| Wider data bus | More bits per transfer | Other components can bottleneck |
Attempt the task before opening its worked response. Record each change of state, explain the rule used, and check the result against the original requirements. Code examples labelled Python 3 use that language’s conventions; pseudocode states its own assumptions.
Common mistakes to avoid
Key takeaways
Test yourself
Answer a few questions, then review anything you missed.
Start with the quiz above to check the key ideas. You can also choose another topic from the practice library.